Digital PLL Design Engineer

Since 1992, Ciena has been driven by a relentless pursuit of network innovation. We believe in a network that grows smarter, more agile, and more responsive every day. This means that when you digitally interact in your world – picking up the phone, streaming video, texting a friend or loved one – your interactions are being enabled by Ciena technologies. Ciena makes your social / entertainment / business existence REAL.

No candidate will meet every single desired qualification. If your experience looks a little different from what we’ve identified below and you think you can bring value to the role, we’d love to learn more about you!

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What will you do at Ciena as a Digital PLL Design Engineer?

The Wavelogic family of products are widely used in Ciena’s optical fiber transmission solutions, and are one of the main contributors to Ciena’s success in the telecommunications industry. To further strengthen our team, we are looking for an enthusiastic digital design engineer who will be involved in the design of these products, working within a team of digital design engineers, verification engineers and architects. Your role as a digital PLL design engineer will be to propose innovative solutions, in order to design power and area optimized timing and synchronization related functional blocks and algorithms for the Wavelogic family of products.

As a digital PLL design engineer, you are expected to read and understand the architecture and functional requirements specification document(s) and communicate and collaborate with systems engineers and architects

You will focus on the digital PLL, jitter, wander and synchronization functions and will define algorithms to extract and propagate source timing and rate information form standard client protocols across the digital optical network.

You will produce an implementation specification document and have it reviewed by your team, architects and analog/board designers if applicable

You are accountable for the creation and integration of new and existing RTL and/or C source code, algorithms and functions

You are responsible for designer testing of your code as well as debugging of your code during simulation, regression and formal verification

You will assist the verification team in determining coverage and provide design assertions and waivers as needed

You are held responsible for crafting timing constraints for your code, and will participate in synthesis log reviews, constraint reviews, timing report analysis, layout and backend reviews

You will be involved in lab validation of the product and its prototype

You are expected to report on status updates on a regular basis

What technical experience and personal skills are required for this role?

Electrical or computer engineering or other applicable scientific degree at the BEng/BSc or MEng/MSc level

Knowledge and experience with system timing and synchronization algorithms, digital PLL design for timing extraction, rate matching, protocol mapping (e.g. GMP, BMP) and FIFO level control

A highly motivated self-starter, able to work independently, while being a great teammate

Ability to methodically solve complex technical problems

Excellent organization, written and oral (English) communication skills

Proficiency above the intermediate level with use of System Verilog for design

Familiarity with digital (including formal) verification methods

Experience with digital design synthesis, STA, timing closure and asynchronous clock crossing

Good understanding of timing/power/area analysis and trade-offs

What additional assets can help me in this role?

Experience with digital ASIC design backend process

Experience with digital design for low power

Experience with standards and protocols such as OTN, B100G, Ethernet, GMP mapping

Experience with using Jira for bug tracking and GIT for source code management and revision tracking

Familiarity with programming languages such as: Python, Make, bash, object-oriented programming, C, C++, System C

The above lists are intended to describe the general nature and level of work, and they are not intended to be a comprehensive list of all responsibilities, duties and skills required to be qualified and to be performed by the selected candidate. You will have an opportunity to better understand the role through the interview experience.

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Being You @ Ciena

As part of our commitment to diversity and inclusion, we want to foster an environment that values and respects all individual’s strengths, perspectives, ideas, and ability to meet the needs of our customers globally. Ciena values the diversity of its workforce and respects its employees as individuals, regardless of race, ethnicity, religion, gender, age, national origin, disability, sexual orientation, veteran or marital status or any other category protected by applicable law. We do not tolerate any form of discrimination. Ciena is also committed to compliance with all fair employment practices regarding citizenship and immigration status. If contacted in relation to a job opportunity, you should advise Ciena in a timely fashion of the specific accommodation measures required for you to be assessed in a fair and equitable manner.

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