Serdes Project Manager

Since 1992, Ciena has been driven by a relentless pursuit of network innovation. We believe in a network that grows smarter, more agile, and more responsive every day. This means that when you digitally interact in your world – picking up the phone, streaming video, texting a friend or loved one – your interactions are being enabled by Ciena technologies. Ciena makes your social / entertainment / business existence REAL.

No candidate will meet every single desired qualification. If your experience looks a little different from what we’ve identified below and you think you can bring value to the role, we’d love to learn more about you!

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What will you do at Ciena as a Serdes project manager?

The Wavelogic family of products is widely used in Ciena’s optical fiber transmission solutions and is one of the main contributors to Ciena’s success in the telecommunications industry. Successful candidates will be joining a vibrant team with a proven track record of success over 30-years of evolution and revolution in the advancement of high-speed circuits used in broadband fiber-optic modems. This team pioneered the introduction of the world’s first high-speed DAC and ADC analog macros that ushered in the era of coherent fiber-optic product solutions.

To further strengthen our team, we are looking for a Serdes project manager who will be involved in organizing the development of advanced high-speed analog circuits in the latest deep-submicron CMOS and/or BiCMOS technologies. As Project Engineering Manager you will participate in the management of mixed-signal IP projects, writing specifications, reviewing planning, and participating in design tasks as required and Ciena’s design methodologies.

The successful candidate will work on a variety of management, and documentation tasks and may also be involved in the design and/or verification tasks, incorporating any specification generation, RTL coding, testbench and test case generation, STA, schematic design, layout, documentation, and prototype evaluation.

Responsibilities

Management of a complex SERDES development project involving multiple teams across the system, analog, digital, packaging, firmware, and test development.

Key responsibilities will include maintaining a top-level schedule overview accounting for sub-deliverables and interdependencies tasks between the teams

Authority to make technical or priority calls for the sub-teams to protect the schedule and quality as well as to prevent work blockages due to inter-team dependencies

On-going tracking of requirements, schedule, and critical task closure through advanced tools such as Jama, Jira, and MS Project.

Convene regular project reviews to ensure sub-teams have a forum to provide progress updates together and to minute these meetings with appropriate tracked action items.

Provide regular high-level program status updates to management highlighting any concerns such as resourcing levels or issues that need to be resolved outside of program-specific decisions

Participate in the complex block and/or chip planning and architecture studies

Create clear project scope documentation and milestone definitions

Convene project kick-off and regular milestones tracking meetings with cross-functional teams

Maintain project plans and resource reports

Participate in design reviews and ensure that all quality checks are completed

Co-ordinate the production of IP Test Chips

Review silicon characterization reports, and design verification reports

Define and co-ordinate IP product releases

Manage product updates triggered silicon process updates, design updates, and customer feedback

Work toward improving design efficiency and achieving the highest possible quality metrics

What technical experience and personal skills are required for this role?

Electrical or computer engineering, computer science, or other applicable scientific degrees at the BEng/BSc, MEng/MSc, or Ph.D. level.

Familiarity with integrated circuit design and design verification.

Experience leading designs in advanced BiCMOS and/or CMOS technology with a minimum of 7-years of industrial experience.

Familiarity with integrated circuit design and design verification.

Familiarity with the development process for ASIC designs.

Familiarity with Project Management and Planning tasks

Good written and verbal communication skills

Familiarity with MS Project and MS Excel

A highly motivated self-starter, able to work independently, while being a great teammate

Ability to methodically address sophisticated technical problems

Excellent organization and interpersonal skills

A history of successful analog circuit product deliveries.

What additional assets can help me in this role?

Experience with 2.5D or 3D E-M tools such as HFSS or EMX

Experience with team leadership within an analog macro design group

Design experience for complex analog macro-IP solutions using tools such as MatLab and/or C++

Experience with mixed-signal design validation using state-of-the-art probing and test equipment

The above lists are intended to describe the general nature and level of work, and they are not intended to be a comprehensive list of all responsibilities, duties, and skills required to be qualified and to be performed by the selected candidate. You will have an opportunity to better understand the role through the interview experience.

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Being You @ Ciena

As part of our commitment to diversity and inclusion, we want to foster an environment that values and respects all individual’s strengths, perspectives, ideas, and ability to meet the needs of our customers globally. Ciena values the diversity of its workforce and respects its employees as individuals, regardless of race, ethnicity, religion, gender, age, national origin, disability, sexual orientation, veteran or marital status or any other category protected by applicable law. We do not tolerate any form of discrimination. Ciena is also committed to compliance with all fair employment practices regarding citizenship and immigration status. If contacted in relation to a job opportunity, you should advise Ciena in a timely fashion of the specific accommodation measures required for you to be assessed in a fair and equitable manner.

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